HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 233

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Chapter 12
Clock, reset, interrupt, timer and
watchdog
March 2003 (rev. A)
Write only registers:
Address
0x1A
0xFF
0x11
0x13
Table 12.2: Overview of the HFC-E1 reset, timer and watchdog registers
Name
R_IRQMSK_MISC
R_IRQ_CTRL
R_TI_WD
A_IRQ_MSK
Number
Table 12.1: Overview of the HFC-E1 clock pins
90
91
92
Name
OSC_IN
OSC_OUT
CLK_MODE
Page
Data Sheet
236
237
238
239
Read only registers:
Address
Description
Oscillator Input Signal
Oscillator Output Signal
Clock Mode
0xCC
0xCD
0xCA
0xCB
0xCE
0xCF
0x1C
0xC8
0xC9
0x10
0x11
Name
R_IRQ_OVIEW
R_IRQ_MISC
R_STATUS
R_IRQ_FIFO_BL0
R_IRQ_FIFO_BL1
R_IRQ_FIFO_BL2
R_IRQ_FIFO_BL3
R_IRQ_FIFO_BL4
R_IRQ_FIFO_BL5
R_IRQ_FIFO_BL6
R_IRQ_FIFO_BL7
Page
240
241
242
243
244
245
246
247
248
249
250
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