HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 153

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
U1
HFC-E1
ADJ_LEV
LEV_A
LEV_B
P W M 1
R_A
R_B
+ 3 . 3 V
G N D
+
C1
1
187
191
190
95
189
188
G N D
5 k 6
1 0 k
R9
R2
1
3
2
U2
LP2980-ADJ
Vin
On/Off
GND
+ 3 . 3 V
G N D
G N D
G N D
G N D
R1
C1
4 7 n
C2
2 2 p
C3
4 7 n
2 2 p
C4
1 0 0 k
R10
C2 and C4 should be located as
near as possible to the R_A and
R_B inputs of the chip.
Vout
ADJ
Figure 5.4: External E1 receive circuitry
Figure 5.5: VDD _ E1 voltage generation
R7
R8
R11
R12
5
4
R13
4 7 0
R3
4 7 0
GND
G N D
R2
E1 interface
Data Sheet
D1
D2
B A V 9 9
B A V 9 9
R1
G N D
+ 2 . 5 V . . . + 3 . 2 V
1 0 0 n
R14
C5
1 5 0
1 5 0
R4
R3
C2
1 n
+ 3 . 3 V
1 0 k
R4
R15
1 5 0
1 5 0
R5
G N D
+
C3
2 2
R16
1 5 0
1 5 0
R6
G N D
C4
1 0 0 n
6
7
8
TR1
UMEC 23014
R X
129
147
164
181
96
HFC-E1
U1
VDD_E1
VDD_E1
VDD_E1
VDD_E1
P W M 0
1 : 1
Cologne
Chip
11
10
9
153 of 272
optional
G N D
C5