HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 137

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

4.3.6 Reading - and -counters
For all asynchronous host accesses to the HFC-E1 there is a small chance that a register is
changed just in the moment when it is read. Because of slightly different delays of individual
bits, it is even possible that the read value is fully invalid. Therefore we advise to read a -
or -counter register until two consecutive readings find the same value.
This is not necessary for a time period of at least 125 s after writing R_FIFO. It is also
not necessary for -counters of receive FIFOs if
received and the counters
March 2003 (rev. A)
HFC-E1
G
For normal data transmission the register A_SUBCH_CFG must be set
to 0x00. To use 56 kbit/s restricted mode for U.S. ISDN lines the register
A_SUBCH_CFG must be set to 0x07 for B-channels.
Important !
FIFO handling and HDLC controller
½´ ¾µ
and
Data Sheet
¾´ ¾µ
are stable and valid.
½
¾
. Then a whole frame has been
Cologne
Chip
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