HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 222

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
The bit value ’0’ executes an access to the external device in Siemens/Intel style. Alterna-
tively an access in Motorola style can be selected with ’1’.
11.2.3 Access mode
The access mode is controlled by the two bit M0 and M1. A normal chip access is done with
M[1..0] = ’00’.
The CIP must be written with one 16 bit access to use the auxiliary interface.
Data write
Data write requires M[1..0] = ’01’ and is always a posted write. An internal write register is
written by the host write access. Then the data is transferred to the auxiliary interface.
Data read
For read operations the auxiliary bridge uses an internal data buffer. The read access can be
performed in three different modes.
Normal read: (M[1..0] = ’01’) In normal read mode a host read access is immediately trans-
Posted read: (M[1..0] = ’10’) Depending on the selected timing for the desired bridge read
Last read: (M[1..0] = ’11’) The last buffered data byte can be read in last read mode. The
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ferred to the auxiliary interface. The host read access must be long enough to pass the
data from the auxiliary interface to the host data bus. Big delays may be involved.
operation, the normal read may not meet the timing requirements of the selected host
interface. To ensure timing constraints when using slow devices the posted read mode
can be selected. In this mode the data of the internal buffer is immediately read by the
host interface. Afterwards a read on the auxiliary interface is initiated to fill the buffer
again. So the data of the first host read access should be ignored.
buffered data is transferred to the host interface and no read access is performed by the
auxiliary bridge afterwards.
/IOR
/DS
0
0
0
1
/IOW
R/
1
0
1
0
Ï
/CS
Table 11.3: Control mode
0
0
0
0
Auxiliary interface
Data Sheet
ALE
1
1
0
0
Operation
read data
write data
read data
write data
Siemens/Intel
Siemens/Intel
Access style
Motorola
Motorola
March 2003 (rev. A)
Cologne
Chip