HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 211

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

9.2 Register description
March 2003 (rev. A)
HFC-E1
R_DTMF0
DTMF configuration register
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
Value
Reset
Name
V_DTMF_EN
V_HARM_SEL
V_DTMF_RX_CH
V_DTMF_STOP
V_CHBL_SEL
(reserved)
V_RESTART_DTMF
V_ULAW_SEL
DTMF controller
(write only)
Data Sheet
Description
Global DTMF enable
’0’ = disable DTMF unit
’1’ = enable DTMF unit
Harmonics selection
2nd harmonics of the DTMF frequencies can be
enabled to improve the detection algorithm.
’0’ = 8 frequencies in 32 channels (only 1st
harmonics are processed)
’1’ = 16 frequencies in 16 channels (1st and 2nd
harmonics are processed)
DTMF data source
’0’ = transmit buffer of the flow controller
(HFC-channels to PCM time slot) are used for
DTMF detection
’1’ = receive buffer of the flow controller
(HFC-channels from PCM time slot) are used for
DTMF detection
Stop DTMF unit
’0’ = continuous DTMF processing
’1’ = DTMF processing stops after Ò processed
samples
HFC-Channel block selection
HFC-Channel block selection (only if 32 channels
are used)
’0’ = lower 16 channels (0 . . . 15)
’1’ = upper 16 channels (16 . . . 31)
Must be ’0’.
Restart DTMF prosessing
’0’ = no action
’1’ = enables new DTMF calculation phase after
stop, automatically cleared
Data coding for DTMF detection
’0’ = A-Law code
’1’ = -Law code
Cologne
Chip
211 of 272
0x1C