HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 19

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Chapter 1
General description
March 2003 (rev. A)
(required for
PCMCIA and
ISA-PnP,
optional for PCI)
128K x 8
512K x 8
EEPROM
SRAM
HFC - E1
Controller
64 FIFOs
32K x 8
RAM
FIFO
for
32 for Receive:
32 for Transmit:
Controllers
HDLC / Transparent
Mode Select
for Channel
HDLC
TM
64
B, D, PCM
B, D, PCM
Universal External Bus Interface
Microprocessor Interface / SPI
FIFO
Figure 1.1: HFC-E1 block diagram
Configuration Registers
Channel
Transmit/Receive
Channel
for FIFO
PCI / ISA-PnP / PCMCIA /
Data Sheet
Processing
Channel
Sub-
Bit Count /
Start Bit /
Mask Bits
Connect
Conference /
DTMF and
Connect
Options
Detect
Confe-
rence
DTMF
Channel
Assigner
Timeslot
Select PCM
Timeslot
Slot
Interface
Bridge
E1
PCM128 /
PCM64 /
PCM30
Interface
19 of 272
E1
(S2M)
CODEC
Select
PCM128
PCM64
PCM30
MST
(IOM2)
(GCI)
8 Bit