HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 250

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
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R_IRQ_FIFO_BL7
FIFO interrupt register for FIFO block 7
In HDLC mode the end of frame is signaled, while in transparent mode the fre-
quency of interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If
a bit is ’0’, no interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register
R_IRQ_OVIEW.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Reset
Value
Name
V_IRQ_FIFO28_TX
V_IRQ_FIFO28_RX
V_IRQ_FIFO29_TX
V_IRQ_FIFO29_RX
V_IRQ_FIFO30_TX
V_IRQ_FIFO30_RX
V_IRQ_FIFO31_TX
V_IRQ_FIFO31_RX
General purpose I/O pins
(read only)
Data Sheet
Interrupt occured in transmit FIFO 28
Interrupt occured in transmit FIFO 29
Interrupt occured in transmit FIFO 30
Interrupt occured in transmit FIFO 31
Description
Interrupt occured in receive FIFO 28
Interrupt occured in receive FIFO 29
Interrupt occured in receive FIFO 30
Interrupt occured in receive FIFO 31
March 2003 (rev. A)
Cologne
Chip
0xCF