HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 234

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
12.1 Clock
The clock generation circuitry of the HFC-E1 is shown in Figure 12.1. Two different crystal
frequencies can be used. Pin CLK_MODE must be set as shown in Table 12.3 to ensure a
system clock of 32,768 MHz.
E1 applications need exactly 32,768 MHz . It is recommended to ensure an accuracy of ¦
50 ppm.
12.2 Reset
HFC-E1 has a level sensitive RESET input. This is low active in PCI mode (pin name
RST#) and high active in all other modes (pin name RESET). The MODE0 / MODE1 pins
must be valid during RESET and /SPISEL must be ’1’ (inactive). After RESET HFC-E1
enters an initialization sequence.
The HFC-E1 has 4 different software resets. The FIFO registers, PCM registers and E1
registers can be reset independently with the bits of the register R_CIRM which are listed in
Table 12.4. The reset bits must be cleared by software.
Information about the registers reset by the different resets can be found in the register list
on pages 16 and 14.
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Crystal frequency
Clock, reset, interrupt, timer and watchdog
U1
HFC-E1
32,768 MHz
65,536 MHz
Figure 12.1: Standard HFC-E1 quartz circuitry
CLK_MODE
OSC_OUT
OSC_IN
Table 12.3: Quartz selection
92
91
90
CLK_MODE
Data Sheet
’1’
’0’
+ 3 . 3 V
G N D
R1
C1
4 7 p
3 2 . 7 6 8 M H z
Q 1
System clock
G N D
32,768 MHz
32,768 MHz
R2
C2
4 7 p
ÄÃÁ
March 2003 (rev. A)
Cologne
Chip