HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 50

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
2.2.3 PCI configuration registers
The PCI configuration space is defined by the configuration register set which is illustrated in
Figure 2.3. In the configuration address space 0x00 . . . 0x47 the PCI configuration register
values are either
The external EEPROM is optional. If no EEPROM is available, the pin EE_SCL/EN has to
be connected to GND and the pin EE_SDA has to be left open. Without EEPROM the PCI
configuration registers will be loaded with the default values shown in Table 2.8.
All configuration registers which can be set by the EEPROM can also be written by config-
uration write accesses to the upper addresses of the configuration register space (from 0xC0
upwards). The addresses for configuration writes are shown in Table 2.8. Unimplemented
registers return all ’0’s when read.
Register Name
Vendor ID
Device ID
Command Register
50 of 272
set by the HFC-E1 default settings of the configuration values or
they can be written to upper configuration registers or
they are read from the external EEPROM.
Address
0x00
0x02
0x04
Universal external bus interface
Width
Word
Word
Word
Table 2.8: PCI configuration registers
Default Value
Data Sheet
0x30B1
0x1397
0x0000
Remarks
Value can be set by EEPROM. Base address
for configuration write is 0xC0.
Value can be set by EEPROM. Base address
for configuration write is 0xC0.
Bits
0
1
5..2
6
7
8
15..9
Function
Enables / disables I/O space accesses
Enables / disables memory space accesses
fixed to 0
PERR# enable / disable
fixed to ’0’
SERR# enable / disable
fixed to 0
(continued on next page)
March 2003 (rev. A)
Cologne
Chip