HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 221

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

11.2 Various mode selections
The host-to-auxiliary bridge can be configured into various modes which define the behavior
of the bridge. The overview of these modes is illustrated in Figure 11.1 and will be described
in the following sections.
11.2.1 Driver mode
The behavior of the data bus of the auxiliary bridge can be modified by V_BRG_MD of the
register R_BRG_PCM_CFG. A ’0’ defines that the bus BRG_D0 . . . BRG_D7 is tristated
when no bridge access is performed and a ’1’ defines that the bus is only tristated when a
read access is performed.
11.2.2 Control mode
The register R_BRG_MD defines for each chip select the style of the access.
March 2003 (rev. A)
HFC-E1
Host
G
As the auxiliary interface and the external SRAM use the same chip pins, it
is strongly recommended not to enable the external SRAM and the bridge
functionality at the same time!
Extract from the register descriptions:
Register
R_CTRL
R_BRG_PCM_CFG
Both register bits are zero by default.
Important !
Host mode
Figure 11.1: Points of contact of the various bridge modes
Bit
V_EXT_RAM
V_BRG_EN
Auxiliary interface
Data Sheet
HFC-E1
Description
The internal SRAM is switched off when ex-
ternal SRAM is used.
’0’ = internal SRAM is used in lower 32 kByte
address space
’1’ = external SRAM is used
’0’ = disable (external SRAM can be used)
’1’ = enable (external SRAM is disabled)
Access mode
chip select
address
control
data
Driver mode
Control mode
Cologne
Chip
221 of 272
external
devices