HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 183

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

6.4 Register description
6.4.1 Write only register
March 2003 (rev. A)
HFC-E1
R_PCM_MD0
PCM mode, register 0
0
1
2
3
7..4
Bits
0
0
0
0
0
Value
Reset
V_PCM_ADDR
Name
V_PCM_MD
V_C4_POL
V_F0_NEG
V_F0_LEN
PCM interface
(write only)
Data Sheet
Description
PCM bus mode
’0’ = slave (pins C4IO and F0IO are inputs)
’1’ = master (pins C4IO and F0IO are outputs)
If no external C4IO and F0IO signal is provided
this bit must be set for operation.
Polarity of C4IO clock
’0’ = pin F0IO is sampled on negative clock
transition of C4IO
’1’ = pin F0IO is sampled on positive clock
transition of C4IO
Polarity of F0IO signal
’0’ = positive pulse
’1’ = negative pulse
Duration of F0IO signal in slave mode
’0’ = active for one C4IO clock (244 ns at 4 MHz)
’1’ = active for two C4IO clocks (488 ns at 4 MHz)
Index value to select the register at address 15
At address 15 a so-called multi-register is
accessible.
0 = R_SL_SEL0 register accessible
1 = R_SL_SEL1 register accessible
2 = R_SL_SEL2 register accessible
3 = R_SL_SEL3 register accessible
4 = R_SL_SEL4 register accessible
5 = R_SL_SEL5 register accessible
6 = R_SL_SEL6 register accessible
7 = R_SL_SEL7 register accessible
9 = R_PCM_MD1 register accessible
0xA = R_PCM_MD2 register accessible
0xC = R_SH0L register accessible
0xD = R_SH0H register accessible
0xE = R_SH1L register accessible
0xF = R_SH1H register accessible
Cologne
Chip
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