HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 49

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.2.2 PCI access description
Two modes exist for register access:
In PCI I/O mapped mode all registers are selected by writing the register address into the
Control Internal Pointer (CIP) register. This is done by writing the HFC-E1 on the higher
I/O addresses (AD2
access must have a width of 16 bit.
All consecutive read or write data accesses (AD2
register is changed.
March 2003 (rev. A)
HFC-E1
1. If HFC-E1 is used in PCI memory mapped mode all registers can directly be accessed
2. In PCI I/O mapped mode HFC-E1 only occupies 8 bytes in the I/O address space.
by adding their CIP address to the configured Memory Base Address.
I/O-Address
I/O-Address+4
C/BE3#
memory
address
0
0
1
1
1
0
0
1
1
C/BE2#
0
1
1
1
0
0
1
1
0
Figure 2.5: PCI access in PCI memory mapped mode
½
DATA 3
DATA 3
Byte 3
Byte 7
Byte 3
). If the auxiliary interface is used (see Chapter 11) the CIP write
Figure 2.4: PCI access in PCI I/O mapped mode
C/BE1#
1
1
0
1
1
1
1
1
1
Universal external bus interface
Table 2.7: PCI command types
C/BE0#
DATA 2
DATA 2
Byte 2
Byte 6
Byte 2
0
0
0
0
0
1
1
1
1
Data Sheet
nibble value
Register
0xC
(PCI bridge only)
0xE
0xA
0xF
0xB
Select
Byte 1
DATA 1
Byte 5
Byte 1
DATA 1
2
6
3
7
¼
) use the selected register until the CIP
I/O Read
Memory Read
Memory Read Multiple
Memory Read Line
Configuration Read
I/O Write
Memory Write
Memory Write and Invalidate
Configuration Write
Command type
Register
DATA 0
DATA 0
Byte 0
Byte 4
Select
Byte 0
}
}
(bytes 4..5)
Data
CIP
Cologne
Chip
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