HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 162

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
162 of 272
R_TX_FR0
E1 time slot 0 configuration, register 0
0
1
2
7..3
Bits
G
The default settings are: V_INV_CLK:
0
0
0
0
Reset
Value
Please note !
Name
V_TRP_FAS
V_TRP_NFAS
V_TRP_RAL
V_TRP_SA
V_EXCHG_DATA_LI: ’0’
V_ATX:
V_NTRI:
(write only)
E1 interface
Data Sheet
Description
Transparent Ë ´
’0’ = Ë bit will be taken from V_TX_FAS
’1’ = HFC-channel 0 data or RAM data will be used
(see V_TX_SL0_RAM of register R_TX_FR2)
Transparent Ë ´Æ
’0’ = Ë bit will be taken from V_TX_NFAS
’1’ = HFC-channel 0 data or RAM data will be used
(see V_TX_SL0_RAM of register R_TX_FR2)
Transparent remote alarm
’0’ = remote alarm bit will be generated internally
from the state machine
’1’ = HFC-channel 0 data or RAM data will be used
(see V_TX_SL0_RAM of register R_TX_FR2)
Transparent Ë
’0’ = Ë bits will be taken from V_TX_SA
’1’ = HFC-channel 0 data or RAM data will be used
(see V_TX_SL0_RAM of register R_TX_FR2)
’0’
’1’
’1’
. . . Ë
˵ bit
˵ bit
bits
March 2003 (rev. A)
Cologne
Chip
0x2C