HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 51

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Register Name
Status Register
Revision ID
Class Code
Header Type
BIST
I/O Base Address
Memory Base Address
Subsystem Vendor ID
Subsystem ID
Cap_Ptr
Interrupt Line
Interrupt Pin
Cap_ID
Next Item Ptr
March 2003 (rev. A)
HFC-E1
Address
0x2C
0x3C
0x0E
0x2E
0x3D
0x08
0x0F
0x10
0x14
0x40
0x41
0x06
0x09
0x34
Universal external bus interface
3 Bytes
DWord
DWord
Width
Word
Word
Word
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Table 2.8: PCI configuration registers
Default Value
Data Sheet
0x020400
0x1397
0x30B1
0x0210
0xFF
0x00
0x01
0x01
0x00
0x40
0x01
0x00
Remarks
HFC-E1 Revision 01
Header type 0
Bits 3 . . . 31 are r/w by configuration ac-
Bits 12 . . . 31 are r/w by configuration ac-
Value can be set by EEPROM. Base address
Value can be set by EEPROM. Base address
This register must be configured by config-
INTA# supported
There are no next items in the linked list.
Bits 0 . . . 7 can be set by EEPROM. Base
address for configuration write is 0xC4.
Bits
3..0
4
5
6
7
8
10..9
11
13..12
14
15
Class code for ‘ISDN controller’.Value can
be set by EEPROM. Base address for con-
figuration write is 0xC8.
No build in self test supported.
cesses. 8 Byte address space is used.
cesses. 4 kByte address space is used.
for configuration write is 0xEC.
for configuration write is 0xEC.
Offset to Power Management register block.
uration write.
Capability ID. 0x01 identifies the linked list
item as PCI Power Management registers.
reserved
’1’ = 66 MHz capable
fault)
’1’ = fast Back-to-Back capable
medium
Function
’1’ = Capabilities List exists, fixed to ’1’
’0’ = 33 MHz capable (default)
reserved
’0’ = fast Back-to-Back not capable (de-
fixed to ’0’
fixed to ’01’: timing of DEVSEL# is
fixed to ’0’
fixed to ’00’
system error (address parity error)
any detected data or system parity error
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Cologne
Chip
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