HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 58

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
control register
58 of 272
¾
: This is an extension to the Plug and Play Specification.
: Only when the isolation process is finished. The last card remains in isolation state until a CSN is assigned.
Card level
address
0x75
G
All ISA registers not implemented return 0x00 when read except the
DMA configuration registers 0x74 and 0x75. These two registers return
0x04 when read. This means no DMA channel has been selected.
Important !
Read / write
Mode
r
Config state
Accessable
Universal external bus interface
Table 2.11: ISA Plug and Play registers
in state
Data Sheet
Description
DMA configuration register 1.
Bits
2..0
7..3
Because no DMA is used this register is hardwired to
0x04.
Function
Select which DMA channel (0 . . . 7) is used for DMA 1.
DMA channel 4, the cascade channel, indicates no DMA
channel is active.
Reserved.
(continued from previous page)
March 2003 (rev. A)
Cologne
Chip