HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 97

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Timed sequence
The data transmission algorithm of the flow controller is FIFO-oriented and handles all FI-
FOs every 125 s in the following sequence
If a faulty configuration writes data from several sources into the same switching buffer, the
last write access overwrites the previous ones. Only in this case it is necessary to know the
process sequence of the flow controller.
The HFC-E1 has three data flow modes. One of them (FIFO sequence mode) is used to
configure a programmable FIFO sequence which can be used instead of the ascending FIFO
numbering. This is explained in Section 3.4.
Transmit operation
In transmit operation one HDLC or transparent byte is read and can be transmitted to the
E1 and the PCM interface as shown in Figure 3.3. Furthermore, data can be transmit-
ted from the E1 interface to the PCM interface. From the flow controller point of view,
the switches select the source for outgoing data.The switches are controlled by the bitmap
V_DATA_FLOW[2..0] of the register A_CON_HDLC[
Receive operation
Figure 3.4 shows the flow controller structure in receive operation. The two switches are
controlled with the bitmap V_DATA_FLOW[2..0]. FIFO data can either be received from
the E1 or PCM interface. Furthermore, data can be transmitted from the PCM interface to
the E1 interface.
March 2003 (rev. A)
HFC-E1
63. FIFO[31,TX]
64. FIFO[31,RX]
1. FIFO[0,TX]
2. FIFO[0,RX]
3. FIFO[1,TX]
4. FIFO[1,RX]
2
. .
.
Due to the FIFO size setup (see Section 4.2) the maximum number of FIFOs might be less than 31.
FIFO data is only transmitted to the E1 interface if V_DATA_FLOW[1] = 0.
The PCM interface can transmit a data byte which comes either from the FIFO or from
the E1 interface. Bit V_DATA_FLOW[2] selects the source for the PCM transmit
slot (see Figure 3.3). The receiving E1 time slot has always the same number as the
transmitting E1 time slot.
The bit V_DATA_FLOW[0] is ignored in transmit operation.
Data Sheet
Data flow
2
:
Ò
,TX] where
Ò
is a FIFO number.
Cologne
Chip
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