HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 235

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Reset name
Soft Reset
HFC Reset
PCM Reset
E1 Reset
Hardware reset
12.3 Interrupt
HFC-E1 is equipped with a maskable interrupt engine. A big variety of interrupt sources can
be enabled and disabled. All interrupts except FIFO interrupts are reported independently of
masking the interrupt or not. Only mask enabled interrupts are used to generate an interrupt
on the interrupt pin of the HFC-E1. Reading the interrupt status register resets the bits.
Interrupt bits set during the reading are reported at the next reading of the interrupt status
registers.
FIFO interrupts can be enabled or disabled by setting the bit V_IRQ in register
A_IRQ_MSK[FIFO]. Because there are 64 interrupts there are 8 interrupt status registers
for FIFO interrupts. To determine which interrupt register must be read in an interrupt rou-
tine there is an interrupt overview register which shows in which status register at least one
interrupt bit is set (R_IRQ_OVIEW). Reading this register does not clear any interrupt. The
following reading of an interrupt register (R_IRQ_FIFO_BL0 . . . R_IRQ_FIFO_BL7)
clears the reported interrupts.
There are some other conditions which also can generate an interrupt. These are reported in
the register R_IRQ_MISC and can be masked in the register R_IRQMSK_MISC.
The R_IRQ_CTRL register sets the behavior of the interrupt output pin. V_GLOB_IRQ_EN
enables the interrupt pin. V_FIFO_IRQ enables the mask enabled FIFO interrupts.
12.4 Watchdog and Timer
The HFC-E1 includes a watchdog and a timer with interrupt capability.
The timer counts F0IO pulses. So the timer is incremented every 125 s. The watchdog
counter is incremented every 2 ms.
The timer values for timer and watchdog can be selected by the R_TI_WD register. 16
different timer and watchdog values can be selected.
The watchdog can be manually reset by setting bit V_WD_RES of the R_BERT_WD_MD
register.
V_AUTO_WD_RES of the R_BERT_WD_MD register is set.
March 2003 (rev. A)
HFC-E1
Furthermore the watchdog is reset at every access to the HFC-E1 if bit
Reset group
H
0
1
2
3
Clock, reset, interrupt, timer and watchdog
Register bit
V_SRES
V_HFCRES
V_PCMRES
V_E1RES
–
Table 12.4: HFC-E1 reset groups
Data Sheet
Description
Hardware reset initiated by RESET input pin
Reset for FIFO, PCM and E1 registers of the HFC-E1. Soft
reset is the same as reset of all partial reset registers.
Reset for all FIFO registers of the HFC-E1.
Reset for all PCM registers of the HFC-E1.
Reset for all E1 registers of the HFC-E1.
Cologne
Chip
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