HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 105

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Channel assigner
The connection between a FIFO and a HFC-channel can be established by the A_CHANNEL
register for each FIFO. For a specified FIFO, the HFC-channel to be connected must be
written to V_CH_NUM0. Typically, the data direction in V_CH_DIR0 is the same as the
FIFO data direction V_FIFO_DIR in the register R_FIFO. With the register settings
the channel assigner connects the nominated FIFO to HFC-channel
A direct connection between a PCM time slot and an E1 time slot allocates one FIFO al-
though this FIFO does not store any data. In Channel Select Mode – in contrast to Simple
Mode – an arbitrary FIFO can be chosen. This FIFO must be enabled to switch on the data
transmission. If there are less than 31 FIFOs in transmit and receive direction, it is necessary
to select an existing FIFO number.
Subchannel Processing
If more than one FIFO is to be connected to one HFC-channel, this HFC-channel number
must be written into the V_CH_NUM0 bitmap of all these FIFOs. In this case every FIFO
contributes one or more bits to construct one HFC-channel byte. Unused bits of a HFC-
channel byte can be set with an arbitrary mask byte.
In transparent mode the FIFO data rate always remains 8 kByte/s. In HDLC mode the FIFO
data rate is determined by the number of bits transmitted to the HFC-channel.
Please see Section 3.5 on page 113 for details concerning the subchannel processor.
Example for CSM
The example of a Channel Select Mode configuration in Figure 3.7 shows four bidirectional
connections (FIFO-to-E1, FIFO-to-PCM, PCM-to-E1 and multiple FIFOs to E1). The black
lines illustrate data paths, whereas the dotted lines symbolize blocked resources. These are
not used for data transmission, but they are necessary to enable the settings.
The following settings demonstrate only the required register values to establish the connec-
tions. All involved FIFOs have to be enabled with V_HDLC_TRP
the register A_CON_HDLC[FIFO]. The non-specified bitmap values depend on the desired
FIFO configuration.
March 2003 (rev. A)
HFC-E1
A_CHANNEL : V_CH_DIR0[FIFO]
FIFO
assigner
assigner
channel
channel
: V_CH_NUM0[FIFO]
Figure 3.6: Channel assigner in CSM
Channel
Data Sheet
Data flow
FIFOs
Ò
V_FIFO_DIR
Assigner
Assigner
channel
channel
Ò
·
.
V_TRP_IRQ
Channel
Cologne
Chip
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