HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 36

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
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Pin
1st function
Interface
2nd function
F1_0
SHAPE0
Name
VDD
GND
C2O
C4IO
F0IO
STIO1
STIO2
GND
VDD
GPI31
GPI30
GPI29
GPI28
NC
VDD_E1
GPIO15
GPIO14
GPIO13
GPIO12
GND
NC
GPI27
GPI26
GPI25
GPI24
GND
IOpu
IOpu
IOpu
IOpu
I/O
IO
IO
IO
IO
O
O
O
I
I
I
I
I
I
I
I
General description
PCM CODEC enable 0
PCM double bit clock I/O
PCM frame clock I/O (8 kHz)
PCM data bus 1, I or O per time
PCM data bus 2, I or O per time
Description
PCM CODEC enable shape sig-
nal 0
+3.3 V power supply
Ground
PCM bit clock output
slot
slot
Ground
+3.3 V power supply
General Purpose Input pin 31
General Purpose Input pin 30
General Purpose Input pin 29
General Purpose Input pin 28
app. +2.8 V power supply (de-
pends on the E1 transmit ampli-
tude)
General Purpose I/O pin 15
General Purpose I/O pin 14
General Purpose I/O pin 13
General Purpose I/O pin 12
Ground
General Purpose Input pin 27
General Purpose Input pin 26
General Purpose Input pin 25
General Purpose Input pin 24
Ground
Data Sheet
GPIO
(continued from previous page)
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
(continued on next page)
March 2003 (rev. A)
Ò
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Cologne
Chip
Á
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16
16
16
16
8
6
8
8
6
8
8
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