HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 189

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_PCM_MD1
PCM mode, register 1
This multi-register is selected with bitmap V_PCM_ADDR = 9 of the register
R_PCM_MD0.
0
1
3..2
5..4
6
7
Bits
0
0
0
0
0
Value
Reset
V_PLL_ADJ
V_PCM_DR
Name
V_CODEC_CON
(reserved)
V_PCM_LOOP
(reserved)
PCM interface
(write only)
Data Sheet
Description
CODEC connection scheme
’0’ = CODEC enable signals on F1_0 . . . F1_7
’1’ = SHAPE 0 pulse on pin SHAPE0, SHAPE 1
pulse on pin SHAPE1 and CODEC count on
F_Q0 . . . F_Q6 for up to 128 external CODECs.
Must be ’0’.
DPLL adjust speed
’00’ = C4IO clock is adjusted in the last time slot
of PCM frame 4 times by one half clock cycle of
PCM clock
’01’ = C4IO clock is adjusted in the last time slot
of PCM frame 3 times by one half clock cycle of
PCM clock
’10’ = C4IO clock is adjusted in the last time slot
of PCM frame twice by one half clock cycle of
PCM clock
’11’ = C4IO clock is adjusted in the last time slot
of PCM frame once by one half clock cycle of
PCM clock
Note: Internal PCM clock is 16.384 MHz nominell
PCM data rate
’00’ = 2 MBit/s (C4IO is 4.096 MHz, 32 time slots)
’01’ = 4 MBit/s (C4IO is 8.192 MHz, 64 time slots)
’10’ = 8 MBit/s (C4IO is 16.384 MHz, 128 time
slots)
’11’ = unused
PCM test loop
When this bit is set, the PCM output data is looped
to the PCM input data internally for all PCM time
slots.
Must be ’0’.
Cologne
Chip
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