HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 242

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
242 of 272
R_STATUS
HFC-E1 status register
0
1
2
3
4
5
6
7
Bits
0
1
0
0
0
0
0
0
Reset
Value
Name
V_BUSY
V_PROC
V_DTMF_IRQSTA
V_LOST_STA
V_SYNC_IN
V_EXT_IRQSTA
V_MISC_IRQSTA
V_FR_IRQSTA
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
BUSY / NOBUSY status
’1’ = the HFC-E1 is BUSY after initialising Reset
FIFO, increment -counter or change FIFO
’0’ = the HFC-E1 is not busy, all accesses are
allowed
Processing / non processing status
’1’ = the HFC-E1 is in processing phase (every
125 s)
’0’ = the HFC-E1 is not in processing phase
DTMF interrupt
DTMF interrupt has occured
LOST error (frames have been lost)
This means the HFC-E1 did not process all data in
125 s. So data may be corrupted.
Bit V_RES_LOST of the R_INC_RES_FIFO
register must be set to reset this bit.
Synchronization input
Value of the SYNC_I input pin
External interrupt
External interrupt has occured
Any miscellaneous interrupt
All enabled miscellaneous interrupts of the register
R_IRQ_MISC are ‘ored’.
Any FIFO interrupt
All enabled FIFO interrupts in the registers
R_IRQ_FIFO_BL0 . . . R_IRQ_FIFO_BL7 are
‘ored’.
March 2003 (rev. A)
Cologne
Chip
0x1C