HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 125

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

(For details on bitmap V_DATA_FLOW see Fig. 3.3 and 3.4 on page 98.)
March 2003 (rev. A)
HFC-E1
A_CON_HDLC [FIFO]
HDLC and connection settings of the selected FIFO
Before writing this array register the FIFO must be selected by register R_FIFO.
0
1
4..2
7..5
Bits
0
0
0
0
Value
Reset
V_TRP_IRQ
V_DATA_FLOW
Name
V_IFF
V_HDLC_TRP
(write only)
Data Sheet
Data flow
Description
Inter frame fill
’0’ = write HDLC flags 0x7F as inter frame fill
’1’ = write all ’1’ s as inter frame fill
Note: For D-channel this bit must be ’1’.
HDLC mode / transparent mode selection
’0’ = HDLC mode
’1’ = transparent mode
Note: For D-channel this bit must be ’0’.
Transparent mode interrupt selection
An interrupt is generated all ¾
[n-1:0] of the ½ - or ¾ -counter become ’1’.
0 = interrupt disabled
1 = all ¾
2 = all ¾
3 = all ¾
4 = all ¾
5 = all ¾
6 = all ¾
7 = all ¾
Note: No interrupt occurs, if the -counters do
never reach the selected values. This depends on
the
Data flow configuration
0 = FIFO ° E1,
1 = FIFO ° PCM, FIFO
2 = FIFO
3 = FIFO ° PCM, PCM
4 = FIFO ° E1,
5 = FIFO
6 = E1 ° PCM,
7 = E1 ° PCM,
Å
¼
¾
setting.
½¾ bytes an interrupt is generated
¾
PCM, E1
E1,
½¼¾ bytes an interrupt is generated
¾¼
½¾ bytes an interrupt is generated
¼
bytes an interrupt is generated
bytes an interrupt is generated
bytes an interrupt is generated
bytes an interrupt is generated
FIFO
E1
E1
E1
PCM
FIFO, PCM
PCM
PCM, PCM
FIFO
FIFO
PCM
E1
E1
Ò
bytes when the bits
Cologne
Chip
125 of 272
FIFO
E1
0xFA