HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 170

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
170 of 272
R_RX_STA0
E1 receive status, register 0
1..0
2
3
5..4
6
7
Bits
0
0
0
0
0
0
Reset
Value
Name
V_RX_STA
V_FR_SYNC
V_SIG_LOS
V_MFA_STA
V_AIS
V_NO_MF_SYNC
E1 interface
(read only)
Data Sheet
Status of multi frame alignment (MFA)
Description
Receive status
’00’ = not synchronized
’01’ = FAS found
’10’ = NFAS found after FAS
’11’ = synchronized (FAS - NFAS - FAS found)
Frame synchronization status
Frame synchronization status according to the state
machine.
LOS status
Loss of receive signal detected.
’01’ = MFA pattern found
’10’ = MFA reached (2 consecutive MFA patterns
found)
Receiving Alarm Indication Signal (AIS)
No multiframe (NMF) synchronization
’1’ = no multiframe synchronization found for
400 ms
This bit is reset by asserting V_RES_NMF of the
register R_RX_FR1.
March 2003 (rev. A)
Cologne
Chip
0x24