HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 61

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

Register Name
Configuration Option
Register (COR)
Card Configuration and
Status Register (CSR)
March 2003 (rev. A)
HFC-E1
Address
0x400
0x402
( : Register address in attribute memory)
Universal external bus interface
Table 2.13: PCMCIA registers
Width
Byte
Byte
Data Sheet
Remarks
5..0
Bit
Bit
0
1
2
3
4
5
6
7
6
7
Rsvd
Intr
PwrDwn
Audio
Rsvd
IOis8
SigChg
Changed
Name
Name
Configuration
Index
LevIREQ
SRESET
Reset
value
0
0
0
0
0
0
0
0
Reset
value
0x00
1
Internal state of interrupt re-
Unimplemented,
Unimplemented,
Function
quest (IREQ#).
Unimplemented,
when read.
when read.
Unimplemented,
when read.
Returns ’0’ when read to indi-
cate an 16 bit data path.
Unimplemented,
when read.
when read.
Function
This bit is not implemented
SRESET card. Setting this
Bit 0 must be set to ’1’
to enable accesses to the
HFC-E1.
and returns always ’1’ when
read to indicate usage of
level mode interrupts.
bit to ’1’ places the card in
the reset state. This bit must
be cleared to zero for nor-
mal operation.
Cologne
Chip
returns ’0’
returns ’0’
returns ’0’
returns ’0’
returns ’0’
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