HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 187

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_SL_SEL4
Slot selection register for pin F1_4
This multi-register is selected with bitmap V_PCM_ADDR = 4 of the register
R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_4 is disabled.
6..0
7
R_SL_SEL5
Slot selection register for pin F1_5
This multi-register is selected with bitmap V_PCM_ADDR = 5 of the register
R_PCM_MD0.
Note: By setting all 8 bits to ’1’ pin F1_5 is disabled.
6..0
7
Bits
Bits
0x7F
1
0x7F
1
Value
Value
Reset
Reset
V_SL_SEL4
V_SL_SEL5
Name
V_SH_SEL4
Name
V_SH_SEL5
PCM interface
(write only)
(write only)
Data Sheet
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 ·½ for
F1_4. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
Description
PCM time slot selection
The selected slot number is V_SL_SEL1 ·½ for
F1_5. Slot number 0 is selected with the maximum
slot number of the selected PCM speed.
Shape selection
’0’ = use shape 0 set by R_SH0L and R_SH0H
registers
’1’ = use shape 1 set by R_SH1L and R_SH1H
registers
Cologne
Chip
187 of 272
0x15
0x15