HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 78

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
In mode 4 (Intel, multiplexed) the states
must be fulfilled to drive data out. The data bus is stable after
after
Address and /BE require a setup time
these lines is
address write is not required.
An 8 bit read access (low byte) is performed in the same way as it is done with 8 bit proces-
sors. Thus see Figure 2.13 for the timing specification.
Symbol
Ø
Ø
Ø
Ø
Ø
Ø
Ø
Ø
78 of 272
Ê
Ä
Ä À
Ë
À
Ê
Ê À
Ä
Ø
½ ¡ Ø
À
.
min / ns
¡ Ø
¡ Ø
¡ Ø
¡ Ø
Ø
À
/BE
ÄÃÁ
ÄÃÁ
ÄÃÁ
ÄÃÁ
ÄÃÁ
. If two consecutive read accesses are on the same address, multiple register
Table 2.23: Symbols of read accesses in Figures 2.13, 2.15 and 2.17
10
10
10
20
20
20
0
2
2
max / ns
’0’
15
( : See ‘Short read method’ on page 67.)
and
Universal external bus interface
/RD+/CS
Characteristic
Address latch time
ALE
Address and /BE valid to /RD+/CS
Address hold time after /RD+/CS
/RD+/CS
Read time:
A[7] = ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
Cycle time between two consecutive /RD+/CS
A[7] = ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
– after byte access
– after word access
´
/RD
Ø
to /WR+/CS
Ë
Data Sheet
·
which starts with the
to data buffer turn on time
to data buffer turn off time
/CS
µ
’0’
and
Ø
setup time
Ñ Ò
/WR
of ALE. The hold time of
and returns into tristate
March 2003 (rev. A)
’1’
Cologne
Chip