HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 248

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
248 of 272
R_IRQ_FIFO_BL5
FIFO interrupt register for FIFO block 5
In HDLC mode the end of frame is signaled, while in transparent mode the fre-
quency of interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If
a bit is ’0’, no interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register
R_IRQ_OVIEW.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Reset
Value
Name
V_IRQ_FIFO20_TX
V_IRQ_FIFO20_RX
V_IRQ_FIFO21_TX
V_IRQ_FIFO21_RX
V_IRQ_FIFO22_TX
V_IRQ_FIFO22_RX
V_IRQ_FIFO23_TX
V_IRQ_FIFO23_RX
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Interrupt occured in transmit FIFO 20
Interrupt occured in transmit FIFO 21
Interrupt occured in transmit FIFO 22
Interrupt occured in transmit FIFO 23
Description
Interrupt occured in receive FIFO 20
Interrupt occured in receive FIFO 21
Interrupt occured in receive FIFO 22
Interrupt occured in receive FIFO 23
March 2003 (rev. A)
Cologne
Chip
0xCD