HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 68

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
8 bit processors write data like shown in Figure 2.10. Timing values are listed in Table 2.21.
/BE3 . . . /BE1 must always be ’1’. /BE0 controls the data bus D7 . . . D0 and can be fixed
to ’0’.
Data is written with
mode 3 (Intel, non-multiplexed). The HFC-E1 requires a data setup time
hold time
Address and /BE0 (if not fixed to low) require a setup time
and byte enable signals are valid. The hold time of these lines is
68 of 272
/WR+/CS
/DS+/CS
/BE[3:1]
D[15:8]
A[7:0]
D[7:0]
/BE0
R/W
/RD
in mode2 only
(Motorola:)
in mode 3 only
(Intel):
Figure 2.10: Write access from 8 bit processors in mode 2 (Motorola) and mode 3 (Intel)
Ø
Ï À
.
t
RWS
of (/DS
t
DWRS
t
t
byte write access
WR
WR
t
data
AS
address
Universal external bus interface
t
·
DWRH
t
RWH
t
AH
/CS) in mode 2 (Motorola) respective (/WR
Data Sheet
permanently high
permanently high
permanently low
t
IDLE
Ø
Ë
which starts when all address
t
RWS
Ø
t
À
DWRS
t
t
byte write access
WR
WR
.
t
data
AS
address
March 2003 (rev. A)
Ø
t
DWRH
t
RWH
Ï Ë
t
AH
Cologne
Chip
·
and a data
/CS) in