HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 180

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
Table 6.3: PCM interface configuration with bitmaps of the register A _ SL _ CFG (The reference numbers relate
to the numbers given in Figure 6.1)
Reference
allow to connect up to eight external CODECs to the HFC-E1. The second way uses the
current time slot number that must be decoded to a CODEC’s select signal. Then up to 128
external CODECs can be connected to the HFC-E1. The choice of these connectivities is
done with V_CODEC_CON of the register R_PCM_MD1.
6.3.1 CODEC select via enable lines
The HFC-E1 has eight CODEC enable signals F1_7 . . . F1_0. Every external CODEC has
to be assigned to a PCM time slot via the bitmaps V_SL_SEL7 . . . V_SL_SEL0 of the
registers R_SL_SEL7 . . . R_SL_SEL0.
Two shape signals can be programmed. The last bit determines the inactive level by which
non-inverted and inverted shape signals can be programmed. Every external CODEC can
choose one of the two shape signals with the bits V_SH_SEL7 . . . V_SH_SEL0 of the
registers R_SL_SEL7 . . . R_SL_SEL0.
Figure 6.2 shows an example with two external CODECs with F1_0 and F1_1 enable sig-
nals. Time slot 0 starts with the F0IO pulse. In this example – assuming that PCM30 is
configured – F1_0 enables the first CODEC on time slot 0 and shape bytes on R_SH0L and
R_SH0H with
and the second CODEC on time slot 1 and shape bytes on R_SH1L and R_SH1H with
180 of 272
[1]
[2]
[3]
[4]
[5]
[6]
[7]
R_PCM_MD0 : V_PCM_ADDR
R_SL_SEL0 : V_SL_SEL0
R_PCM_MD0 : V_PCM_ADDR
R_SL_SEL1 : V_SL_SEL1
Function
Enable memory read for transmit slot
HFC-channel select for transmit slot
STIO1 output buffer enable for transmit slot
STIO2 output buffer enable for transmit slot
Input buffer select for receive slot
HFC-channel select for receive slot
Enable memory write for receive slot
: V_SH_SEL0
: V_SH_SEL1
PCM interface
0x1F
0
Data Sheet
0
0
1
1
(MUX A)
(MUX B)
(MUX C)
(time slot #1)
(R_SL_SEL1 register accessible)
(shape bytes R_SH1L and R_SH1H)
(time slot #0)
(R_SL_SEL0 register accessible)
(shape bytes R_SH0L and R_SH0H)
V_ROUT
V_ROUT
V_ROUT
V_CH_NUM1
V_ROUT
V_CH_NUM1
V_ROUT
Bitmap
V_ROUT
V_ROUT
’01’ (Loop PCM internally)
’10’ (Data In from STIO1)
’11’ (Data In from STIO2)
March 2003 (rev. A)
0 . . . 31
0 . . . 31
Value
’10’
’11’
’00’
’00’
Cologne
Chip