HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 181

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

The shown shape signals have to be programmed in reverse bit order by
6.3.2 CODEC select via time slot number
Alternatively, external CODECs can be enabled by decoding the time slot number. In this
case, two programmable shape signals SHAPE0 and SHAPE1 are put out with every time
slot. The current time slot number is issued on the pins F_Q6 . . . F_Q0.
The shape signals can be programmed. The example in Figure 6.3 shows shape signals that
are programmed in the same way as shown above (see Section 6.3.1).
F_Q6 . . . F_Q0 must be decoded externally to generate CODEC select signals in depen-
dence on the PCM time slot.
March 2003 (rev. A)
HFC-E1
F0IO
C4IO
F1_0
F1_1
C2O
bit
slot
LSB
0
0 0 1 1 1
Figure 6.2: Example for two CODEC enable signal shapes with SHAPE0 and SHAPE1.
1
R_PCM_MD0 : V_PCM_ADDR
R_SH0L
R_PCM_MD0 : V_PCM_ADDR
R_SH0L
R_PCM_MD0 : V_PCM_ADDR
R_SH0L
R_PCM_MD0 : V_PCM_ADDR
R_SH0L
low byte
0
1
1 1 1 0 0 0
: V_SH0L
: V_SH0L
: V_SH0L
: V_SH0L
7
high byte
0 0 0
6
MSB
5
PCM interface
16 C4IO pulses per slot
8 C2O pulses per slot
0xF8
0x03
0x1F
0xF0
Data Sheet
0xC
0xD
0xE
0xF
4
0
3
(R_SH0L register accessible)
(0xF8 = ’11111000’
(R_SH0H register accessible)
(0x03 = ’00000011’
(R_SH1L register accessible)
(0x1F = ’00011111’
(R_SH1H register accessible)
(0xF0 = ’11110000’
2
LSB
1
1 1 1 1 0
1
low byte
Ö Ú Ö×
Ö Ú Ö×
Ö Ú Ö×
Ö Ú Ö×
0
0
0 0 0 0 0 1
’00011111’)
’11000000’)
’11111000’)
’00001111’)
7
high byte
1
Cologne
Chip
181 of 272
1 1 1
6
MSB