HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 215

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

10.2 Register description
10.3 Write only register
March 2003 (rev. A)
HFC-E1
R_BERT_WD_MD
Bit error rate test (BERT) and watchdog mode
2..0
3
4
5
6
7
Bits
0
0
0
0
Value
Reset
V_PAT_SEQ
Name
V_BERT_ERR
(reserved)
V_AUTO_WD_RES
(reserved)
V_WD_RES
(write only)
Data Sheet
BERT
Description
Pattern for BERT
’000’ = continuous ’0’ pattern
’001’ = continuous ’1’ pattern
’010’ = pseudo random pattern seq. ¾ ½
’011’ = pseudo random pattern seq. ¾
’100’ = pseudo random pattern seq. ¾
’101’ = pseudo random pattern seq. ¾
’110’ = pseudo random pattern seq. ¾
maximal 14 bits are zero
’111’ = pseudo random pattern seq. ¾
Note: This sequences are defined in ITU-T O.150
and O.151 specifications.
BERT error
Generates 1 error bit in the BERT data stream
’0’ = no error generation
’1’ = generates one error bit
This bit is cleared automatically.
Must be ’0’.
Automatically watchdog timer reset
’0’ = watchdog is only reset by V_WD_RES
’1’ = watchdog is reset after every access to the chip
Must be ’0’.
Watchdog timer reset
’0’ = no action
’1’ = manual watchdog timer reset
This bit is automatically cleared.
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¼
½
½
½
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Cologne
Chip
215 of 272
0x1B