HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 69

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.5.2.2 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
16 bit processors can either read data with byte or word access like shown in Figure 2.11.
FIFO and - / -counter read access have 8 bit or 16 bit width alternatively. The 16 bit pro-
cessor must support byte access because all other register read accesses must have a width
of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 switch the data bus D15 . . . D0 from
tristate into data driven state (see Table 2.19).
Data can be read in mode 2 (Motorola) with
March 2003 (rev. A)
HFC-E1
/DS+/CS
/RD+/CS
/BE[3:2]
D[15:8]
A[7:0]
D[7:0]
Figure 2.11: Byte and word read access from 16 bit processors in mode 2 (Motorola) and mode 3 (Intel)
/BE1
/BE0
R/W
/WR
in mode2 only
(Motorola:)
in mode 3 only
(Intel):
/BE
word read access
t
AS
byte enable
byte enable
t
RWS
address
’0’
t
t
DRDZ
DRDZ
t
RD
t
RDmin
data
data
and
t
Universal external bus interface
t
t
t
AH
DRDH
DRDH
RWH
´
/DS
t
CYCLE
Data Sheet
·
low byte read access
/CS
permanently high
permanently high
t
AS
byte enable
byte enable
µ
t
RWS
address
t
DRDZ
t
RD
’0’
t
RDmin
data
t
t
t
AH
and
DRDH
RWH
R/W
t
CYCLE
high byte read access
t
AS
’1’
byte enable
byte enable
t
RWS
address
t
DRDZ
t
RD
t
RDmin
data
Cologne
Chip
t
69 of 272
t
AH
RWH
t
DRDH