HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 123

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

(See Figure 6.1 on page 179 for detailed information).
March 2003 (rev. A)
HFC-E1
A_SL_CFG [SLOT]
HFC-channel assignment for the selected PCM time slot and PCM output buffer
configuration
With this register a HFC-channel can be assigned to the selected PCM time slot.
Additionally, the PCM buffers can be configured.
Before writing this array register the PCM time slot must be selected by the reg-
ister R_SLOT.
0
5..1
7..6
Bits
0
0
0
Value
Reset
V_CH_NUM1
V_ROUT
Name
V_CH_DIR1
(write only)
Data Sheet
Data flow
Description
HFC-channel data direction
’0’ = HFC-channel for transmit data
’1’ = HFC-channel for receive data
HFC-channel number
(0 . . . 31)
PCM output buffer configuration
For transmit time slots:
’00’ = disable output buffers, no data transmision
’01’ = transmit data internally, output buffers
disabled
’10’ = output buffer enable for STIO1
’11’ = output buffer enable for STIO2
For receive time slots:
’00’ = input data is ignored
’01’ = loop PCM data internally
’10’ = data in from STIO2
’11’ = data in from STIO1
Cologne
Chip
123 of 272
0xD0