HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 89

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_RAM_MISC
RAM size setup and miscellaneous functions register
1..0
3..2
4
5
6
7
Bits
0
0
0
0
Value
Reset
V_RAM_SZ
(reserved)
Name
V_PWM0_16KHZ
V_PWM1_16KHZ
(reserved)
V_FZ_MD
Universal external bus interface
(write only)
Data Sheet
Description
RAM size
’00’ = 32k x 8
’01’ = 128k x 8
’10’ = 512k x 8
’11’ = reserved
After setting V_RAM_SZ to a value different from
’00’ a soft reset should be initiated.
Must be ’00’.
16 kHz signal on pin PWM0
’0’ = normal PWM0 function
’1’ = 16 kHz output
16 kHz signal on pin PWM1
’0’ = normal PWM1 function
’1’ = 16 kHz output
Must be ’0’.
Exchange - / -counter context
(for transmit FIFOs only)
’0’ = A_Z1L, A_Z1H = ½´ ½µ and A_Z2L,
A_Z2H = ¾´ ½µ (normal operation)
’1’ = A_Z1L, A_Z1H = ½´ ½µ and A_Z2L,
A_Z2H = ¾´ ¾µ (exchanged operation)
This bit can be used to check the actual RAM usage
of transmit FIFOs.
Cologne
Chip
89 of 272
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