HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 225

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

11.3 Timing definitions
The timing requirements of the connected external devices can be fulfilled by programming
different timing configurations. Four different read and write timings can be programmed in
the registers R_BRG_TIM0 . . . R_BRG_TIM3.
The timings are defined by writing the number of idle clock cycles for an access to the
bitmaps V_BRG_TIM0_IDLE . . . V_BRG_TIM3_IDLE of the registers R_BRG_TIM0
. . . R_BRG_TIM3.
V_BRG_TIM0_CLK . . . V_BRG_TIM3_CLK of the same registers.
The timing can be configured for each chip select and read / write operation independently
by programming the registers R_BRG_TIM_SEL01 . . . R_BRG_TIM_SEL67.
March 2003 (rev. A)
HFC-E1
The number of active clock cycles are defined in the bitmaps
Auxiliary interface
Data Sheet
Cologne
Chip
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