HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 224

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
Bridge access in memory mapped mode
This mode is supported for PCI memory mapped mode and processor mode.
In memory mapped mode the control register R_BRG_CTRL can be used to perfom read
and write accesses with a large address space. External devices with up to 10 address lines
do not require this register. If R_BRG_CTRL is not used, the exact number of available
address lines depends on the number of external devices. An overview of this functionality
is given in Figure 11.3.
V_BRG_CS_SRC of the register R_BRG_CTRL selects the source of the chip select
signals. By default the address lines 7 . . . 9 are taken.
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Host
1. If the external devices have not more than 7 address lines, the register R_BRG_CTRL
2. External devices with 8 . . . 10 address lines take one, two or even all chip select lines
3. The full 12 bit address space can be used with the bitmap V_BRG_ADDR of the reg-
R_BRG_CTRL
V_BRG_CS
V_BRG_ADDR
V_BRG_CS_SRC
is not necessary for bridge accesses. The bridge operation can be performed with 12
address bits as shown in Figure 11.3. Up to 8 external devices can be connected to the
HFC-E1.
CS[0..2] from the address specification bits. The number of chip select output signals
on the pins /BRG_CS0 . . . /BRG_CS7 is reduced appropriately. If A[7] . . . A[9] are
used in parallel to chip select signals, the bit V_BRG_CS_SRC must be set in the
register R_BRG_CTRL.
ister R_BRG_CTRL. The address bits A[10] and A[11] have to be specified there.
register and address bytes
0..2
3..4
10
11
7
0
1
2
3
4
5
6
7
8
9
Figure 11.3: Host bridge structure in memory mapped mode
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7],CS[0]
A[8],CS[1]
A[9],CS[2]
M[0]
M[1]
CS[0..2]
A[10,11]
Auxiliary interface
Data Sheet
HFC-E1
0
1
3
12
/BRG_CS[0..7]
CS[0..2]
Demultiplexer
BRG_A[0..11]
BRG_D[0..7]
Access
mode
/BRG_WR
/BRG_RD
0
7
connected pins
8
2
up to
12
8
2
March 2003 (rev. A)
address
data
control
chip select
address
data
control
chip select
address
data
control
chip select
Cologne
Chip
device #0
device #1
device #7
external
external
external