HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 229

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_BRG_TIM0
Auxiliary bridge timing configuration register for timing 0
3..0
7..4
R_BRG_TIM1
Auxiliary bridge timing configuration register for timing 1
3..0
7..4
Bits
Bits
0
0
0
0
Value
Value
Reset
Reset
V_BRG_TIM0_IDLE
V_BRG_TIM0_CLK
V_BRG_TIM1_IDLE
V_BRG_TIM1_CLK
Name
Name
Auxiliary interface
(write only)
(write only)
Data Sheet
Description
Idle cycles
Number of idle system clock cycles for read / write
signal
Active cycles
Number of active system clock cycles for
read / write signal
Description
Idle cycles
Number of idle clock cycles for read / write signal
Active cycles
Number of active clock cycles for read / write signal
Cologne
Chip
229 of 272
0x48
0x49