HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 131

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

The reset state of the - and -counters is
This initialization can be carried out with a soft reset or a HDLC reset. For this, the bit
V_SRES or the bit V_HFCRES in the register R_CIRM have to be set. Individual FIFOs
can be reset with bit V_RES_F of the register R_INC_RES_FIFO.
In addition, a hardware reset initializes the counters.
4.2 FIFO size setup
The HFC-E1 can operate with 32k x 8 internal or alternatively with 128k x 8 or 512k x 8
external SRAM. The bitmap V_RAM_SZ of the register R_RAM_MISC must be set ac-
cordingly to the RAM size. Table 4.3 shows how the FIFO size can be varied with the
different RAM sizes. Additionally, the initial
After changing the FIFO size or RAM size a soft reset should be initiated.
March 2003 (rev. A)
HFC-E1
1
2
See
See
½
½
G
Busy status after FIFO change, FIFO reset and
tion
Changing a FIFO, reseting a FIFO or incrementing the -counters causes
a short BUSY period of the HFC-E1. This means an access to FIFO
control registers is not allowed until BUSY status is reset (bit V_BUSY
of R_STATUS register). The maximum duration takes 25 clock cycles
( 1 s). Status, interrupt and control registers can be read and written at
any time.
G
The counter state
follows counter state
Please note that
size (s. Section 4.2 and Table 4.3).
Ü
Ü
value in Table 4.2.
value in Table 4.3.
Important !
Please note !
¾
¾
Å
Å
1
2
.
and
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FIFO handling and HDLC controller
ÅÁÆ
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and
(resp.
(resp.
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Data Sheet
ÅÁÆ
depend on the FIFO number and FIFO
) of the -counters (resp. -counters)
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) in the FIFOs.
and
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values are given in Table 4.3.
½
/
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incrementa-
Cologne
Chip
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