HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 70

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
In mode 3 (Intel, non-multiplexed) the states
must be fulfilled to drive data out. The data bus is stable after
after
Address and /BE require a setup time
signals are valid. The hold time of these lines is
Symbol
Ø
Ø
Ø
Ø
Ø
Ø
Ø
Ø
70 of 272
ÊÏË
ÊÏÀ
Ê
Ë
À
Ê
Ê À
Ä
Ø
½ ¡ Ø
À
.
min / ns
¡ Ø
¡ Ø
¡ Ø
¡ Ø
/BE
ÄÃÁ
ÄÃÁ
ÄÃÁ
ÄÃÁ
ÄÃÁ
10
10
20
20
2
2
2
2
Table 2.20: Symbols of read accesses in Figures 2.9 and 2.11
max / ns
’0’
15
A[0]
Table 2.19: Data access width in mode 2 and 3
’X’
’0’
’1’
’0’
( : See ‘Short read method’ on page 67.)
and
Universal external bus interface
/DS+/CS (/RD+/CS)
Characteristic
Address and /BE valid to /DS+/CS (/RD+/CS)
Address hold time after /DS+/CS (/RD+/CS)
/DS+/CS (/RD+/CS)
R/W setup time to /DS+/CS
R/W hold time after /DS+/CS
Read time:
A[7] = ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
Cycle time between two consecutive /DS+/CS (/RD+/CS)
A[7] = ’0’ (address range 0 . . . 0x7F: normal register access)
A[7,6] = ’10’ (address range 0x80 . . . 0xBF: FIFO data access)
A[7,6] = ’11’ (address range 0xC0 . . . 0xFF: direct RAM access, FIFO
interrupt registers)
/BE1
’1’
’0’
’0’
’1’
– after byte access
– after word access
´
/RD
/BE0
Ø
’1’
’0’
’1’
’0’
Data Sheet
·
Ë
which starts when all address and byte enable
/CS
Data access
no access
byte access on D[7:0]
byte access on D[15:8]
word access
µ
Ø
À
to data buffer turn on time
to data buffer turn off time
.
’0’
and
Ø
Ñ Ò
/WR
and returns into tristate
March 2003 (rev. A)
setup time
’1’
Cologne
Chip