HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 81

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.5.3 Examples of processor connection circuitries
March 2003 (rev. A)
HFC-E1
ADDRESS / DATA
8 bit Processor
8 bit Processor
Figure 2.19: 8 bit Intel / Motorola processor circuitry example (mode 2)
CONTROL
8 b i t P r o c e s s o r
( M o t o r o l a M o d e )
RESET
Universal external bus interface
/WD
R/W
/INT
D07
D06
D05
D04
D03
D02
D01
D00
A07
A06
A05
A04
A03
A02
A01
A00
/DS
/CS
R * c a n b e o m i t t e d i f r e s e t
i s a c t i v e d u r i n g p o w e r o n .
Data Sheet
R1
R2
+ 3 . 3 V
+ 3 . 3 V
+ 3 . 3 V
R*
R*
R*
d e p e n d s o n
a p p l i c a t i o n
R3
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
R*
G N D
G N D
G N D
1 M
1 M
1 M
+ 3 . 3 V
+ 3 . 3 V
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
1 M
G N D
R*
G N D
+ 3 . 3 V
G N D
G N D
n c
n c
n c
196
195
194
197
100
198
200
203
204
205
206
99
26
25
23
24
21
22
20
27
18
30
40
10
11
14
15
16
17
31
32
33
34
36
37
38
39
43
44
45
46
48
49
50
51
7
6
1
2
3
4
8
9
HFC-E1
( P r o c e s s o r i n t e r f a c e ,
m o d e 2 , M o t o r o l a )
NC
GND
VDD
/INT
M O D E 0
M O D E 1
RESET
GND
NC
/BUSDIR
GND
/WD
ALE
/IOR
/ I O W
/CS
FL0
/BE3
/BE2
/BE1
/BE0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
U1
Cologne
Chip
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