HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 111

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

The FIFO sequence list terminates with V_SEQ_END
The other list entries must set V_SEQ_END
the next entry.
Example for FSM
Figure 3.10 shows an example with three bidirectional connections. The black lines illustrate
data paths, whereas the dotted lines symbolize blocked HFC-channels. These are not used
for data transmission, but they are necessary to enable the settings.
All FIFOs can be arranged in arbitrary order. In the example the list specification of Table 3.4
is chosen. To select FIFO[12,TX] as first FIFO R_FIRST_FIFO is set as follows:
March 2003 (rev. A)
HFC-E1
➊ FIFO-to-E1
The bidirectional FIFO-to-E1 connection allocates the list indices 0 and 1 as follows:
FIFOs
#14
#14
#12
#12
#13
#13
R_FIRST_FIFO : V_FIRST_FIFO_DIR
RX
RX
TX
RX
TX
TX
: V_FIRST_FIFO_NUM
Figure 3.10: FSM example
1
3
2
Data Sheet
HFC-channel
Data flow
0
12
¼
#12
#12
#17
#17
#20
#20
#15 TX
#15 RX
to continue the sequence processing with
RX
RX
RX
TX
TX
TX
(transmit FIFO)
(FIFO #12)
½
in the register A_FIFO_SEQ.
#12
#12
#17
#17
#20
#20
#15
#15
#21
#21
PCM slot
E1 slot
RX
RX
RX
RX
RX
TX
TX
TX
TX
TX
Cologne
Chip
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