HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 47

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.2 PCI interface
The PCI mode is selected by MODE0
are supported by the HFC-E1.
5 V PCI bus signaling environment is supported with 3.3 V supply voltage of the HFC-E1.
Never connect the power supply of the HFC-E1 to 5 V!
The PCI interface is build according to the PCI Specification 2.2.
2.2.1 PCI command types
Table 2.7 shows the supported PCI commands of the HFC-E1.
Memory Read Line and Memory Read Multiple commands are aliased to Memory Read.
Memory Write and Invalidate is aliased to Memory Write.
March 2003 (rev. A)
HFC-E1
203 . . . 206, 1 . . . 4
6, 18, 30, 40
Number
31 . . . 39
43 . . . 51
8 . . . 17
195
196
197
198
200
20
21
22
23
24
25
26
27
Table 2.6: Overview of the PCI interface pins
7
Universal external bus interface
Name
AD31 . . . AD24
AD23 . . . AD16
AD15 . . . AD8
AD7 . . . AD0
C/BE3# . . . C/BE0#
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PME_IN
PME
INTA#
RST#
PCICLK
¼
Data Sheet
and MODE1
Address / Data byte 3
Address / Data byte 2
Address / Data byte 1
Address / Data byte 0
Bus command and Byte Enable 3 . . . 0
Initialisation Device Select
Target Ready
Device Select
Description
Cycle Frame
Initiator Ready
Stop
Parity Error
System Error
Parity Bit
Power Management Event Input
Power Management Event output
Interrupt request
Reset low active
PCI Clock Input
¼
. Only PCI target mode accesses
Cologne
Chip
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