HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 98

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
98 of 272
Bit V_DATA_FLOW[0] selects the source for the receive FIFO which can either be
the PCM or the E1 interface.
Furthermore, the received PCM byte can be transferred to the E1 interface. This re-
quires bit V_DATA_FLOW[1] = 1.
The bit V_DATA_FLOW[2] is ignored in receive FIFO operation.
channel data from
channel data from
HDLC controller
HDLC controller
HDLC controller
HDLC controller
channel data to
channel data to
transparent
transparent
HDLC or
HDLC or
data
data
Figure 3.4: The flow controller in receive FIFO operation
Figure 3.3: The flow controller in transmit operation
no data
transfer
no data
transfer
Flow Controller
in transmit operation
Flow Controller
in receive operation
receive FIFO
selection
V_DATA_FLOW [0]
0
1
Data Sheet
Data flow
transmit PCM
selection
transmit S/T
selection
transmit S/T
selection
0
1
0
1
0
1
V_DATA_FLOW [1]
V_DATA_FLOW [2]
V_DATA_FLOW [1]
switching buffer
switching buffer
switching buffer
switching buffer
switching buffer
switching buffer
no data
transfer
no data
transfer
March 2003 (rev. A)
channel data from
transmit PCM slot
channel data from
channel data from
transmit PCM slot
channel data from
receive PCM slot
receive PCM slot
channel data to
transmit E1 slot
channel data to
channel data to
transmit E1 slot
channel data to
receive E1 slot
receive E1 slot
Cologne
Chip