HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 226

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
11.4 Register description
226 of 272
R_BRG_PCM_CFG
Auxiliary bridge and PCM configuration register
0
1
4..2
5
7..6
Bits
0
0
0
0
Reset
Value
Name
V_BRG_EN
V_BRG_MD
(reserved)
V_PCM_CLK
(reserved)
Auxiliary interface
(write only)
Data Sheet
Must be ’00’.
Description
Auxiliary bridge enable
’0’ = disable (external SRAM can be used)
’1’ = enable (external SRAM is disabled)
Auxiliary bridge data lines mode
Mode of the data bus pins SRD0 SRD7.
’0’ = tristate when no bridge access
’1’ = only tristate when data is read
Must be ’000’.
Clock of the PCM module
’0’ = system clock / 2
’1’ = system clock / 4
PCM clock must be 16.384 MHz, system clock is
normaly 24.576 MHz.
March 2003 (rev. A)
Cologne
Chip
0x02