HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 171

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_RX_STA1
E1 receive status, register 1
0
1
2
3
4
5
6
7
R_RX_STA2
E1 receive status, register 2
3..0
5..4
6
7
Bits
Bits
0
0
0
0
0
0
0
0
0
0
0
Value
Value
Reset
Reset
V_SA6
(reserved)
Name
V_SI_FAS
V_SI_NFAS
V_A
V_CRC_OK
V_TX_E1
V_TX_E2
V_RX_E1
V_RX_E2
Name
V_SA6_OK
V_SA6_CHG
E1 interface
(read only)
(read only)
Data Sheet
Description
Ë ´
Ë ´Æ
A-bit of time slot 0
CRC result
’1’ = CRC4 ok
Transmit CRC4 E1-bit
Transmit CRC4 E2-bit
Receive CRC4 E1-bit
Receive CRC4 E2-bit
Description
Ë
Ë
The same value was received in 3 consecutive
SMFs.
Ë
This bit is automatically reset after register read.
OK
pattern has changed
˵ in time slot 0
½ bits of time slot 0
˵ in time slot 0
Cologne
Chip
171 of 272
0x25
0x26