HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 239

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
A_IRQ_MSK [FIFO]
Interrupt register for the selected FIFO
Before writing this array register the FIFO must be selected by register R_FIFO.
0
1
2
7..3
Bits
0
0
0
Value
Reset
Name
V_IRQ
V_BERT_EN
V_MIX_IRQ
(reserved)
Clock, reset, interrupt, timer and watchdog
(write only)
Data Sheet
Description
Interrupt mask for the selected FIFO
’0’ = disabled
’1’ = enabled
BERT output enable
’0’ = BERT disabled, normal data is transmitted
’1’ = BERT enabled, output of BERT generator is
transmitted
Mixed interrupt generation
’0’ = disabled (normal operation)
’1’ = frame interrupts and transparent interrupts are
both generated in HDLC mode
Must be ’00000’.
Cologne
Chip
239 of 272
0xFF