HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 88

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
88 of 272
R_RAM_ADDR1
Address pointer, register 1
2nd address byte for internal / external SRAM access.
7..0
R_RAM_ADDR2
Address pointer, register 2
High address bits for internal / external SRAM access and access configuration.
3..0
5..4
6
7
Bits
Bits
0x00
0
0
0
Reset
Value
Reset
Value
Name
V_RAM_ADDR1
Name
V_RAM_ADDR2
(reserved)
V_ADDR_RES
V_ADDR_INC
Universal external bus interface
(write only)
(write only)
Data Sheet
Address bits 15 . . . 8
Address bits 19 . . . 16
Must be ’00’.
Description
Description
Address reset
’0’ = normal operation
’1’ = address bits 0 . . . 15 are set to zero
This bit is automatically cleared.
Address increment
’0’ = no address increment
’1’ = automatically increment of the address after
every write or read on register R_RAM_DATA
March 2003 (rev. A)
Cologne
Chip
0x0A
0x09