HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 168

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
168 of 272
R_SYNC_CTRL
E1 transmit clock sychronization register
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Reset
Value
Name
V_EXT_CLK_SYNC
V_SYNC_OFFS
V_PCM_SYNC
V_NEG_CLK
V_HCLK
V_JATT_AUTO_DEL
V_JATT_AUTO
V_JATT_EN
(write only)
E1 interface
Data Sheet
Restricted frequency search
Automatic JATT adjustment
Description
E1 synchronization source selection
’0’ = clock synchronization derived from receive
data
’1’ = synchronization is determined from
V_PCM_SYNC, V_NEG_CLK and V_HCLK
E1 synchronization type selection
’0’ = TX and RX frame synchronization phase
offset 0
’1’ = TX and RX frame synchronization phase
offset arbitrary
Note: If this bit is set the synchronization process
is faster because the phase offset can be arbitrary.
E1 synchronization source select
’0’ = pin SYNC_I
’1’ = synchronization from PCM pin F0IO
External synchronization clock polarity
’0’ = positive edge
’1’ = negative edge
Half clock frequency
’0’ = normal operation
’1’ = external synchronization clock will be divided
by 2
’0’ = automatic frequency search is initiated after 3
frequency mismatches every 0.5 s
’1’ = automatic frequency search is initiated after
10 frequency mismatches every 0.5 s
’0’ = automatic JATT adjust enabled
’1’ = automatic JATT adjust disabled
JATT enable
’0’ = JATT enabled
’1’ = JATT disabled (transmit clock is generated
from crystal clock)
March 2003 (rev. A)
Cologne
Chip
0x35