HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 83

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

2.6 Serial processor interface (SPI)
The SPI interface mode is selected by MODE0 = 1, MODE1 = 0 and connecting pin 200 to
SPI clock. /SPISEL must be high during reset. The first positive edge on SPICLK switches
the interface from processor interface mode into SPI mode. This may be the first positive
clock at the start of an SPI access.
The interface has 4 pins as shown in Table 2.25. For further information please see the SPI
specification.
2.6.1 SPI read and write access
In SPI mode each data transfer is 16 bit long. From the first 8 bits only the bits
8 bits are read from the HFC-E1 or written into the HFC-E1 as shown in the Figures 2.21
and 2.22. So all data accesses in SPI mode handle 8 data bits.
It is allowed to interrupt the /SPISEL signal between the two bytes. In this case the trans-
mission pauses and will be continued after /SPISEL returns to low level. An example for an
interrupted read access is shown in Figure 2.23.
March 2003 (rev. A)
HFC-E1
/SPISEL
SPICLK
SPI_RX
SPI_TX
Ê
don’t care
don’t care R/W
Ì
are used. The other 6 bits must be zero. Depending on the
A/D
Number
Table 2.25: Overview of the SPI interface pins
1st_byte
194
195
196
197
198
200
Universal external bus interface
6 bit low
Figure 2.21: SPI read access
Name
/SPISEL
SPI_RX
SPI_TX
/INT
RESET
SPICLK
Data Sheet
Description
SPI device select low active
SPI receive data input
SPI transmit data output
Interrupt request
Reset high active
SPI clock input
D7
D6
D5
2nd_byte
D4
don’t care
D3
Ê Ï
D2
D1
bit the second
Cologne
Chip
D0
Ê Ï
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