HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 135

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

for HFC-E1 to manage more frames even if the frames are very small. The second limitation
is the overall size of the FIFO.
4.3.3 HDLC receive FIFOs
The receive HFC-channels receive data from the E1 or PCM bus interface read registers. The
data is converted from HDLC into plain data and sent to the FIFO. The data can then be read
via the host bus interface.
The HFC-E1 checks the HDLC data coming in. If it finds a flag or more than 5 consecutive
’1’s it does not generate any output data. In this case
data being received is converted by the HFC-E1 into plain data. After the ending flag of a
frame the HFC-E1 checks the HDLC CRC checksum. If it is correct one byte with all ’0’s
is inserted behind the CRC data in the FIFO named STAT (see Fig. 4.2). This last byte of a
frame in the FIFO is different from all ’0’s if there is no correct CRC field at the end of the
frame.
If the STAT value is 0xFF, the HDLC frame ended with at least 8 bits ’1’s. This is similar to
an abort HDLC frame condition.
The ending flag of a HDLC frame can also be the starting flag of the next frame.
After a frame is received completely
the next frame can be received.
After reading a frame via the host bus interface
counter
of
HFC-E1.
interface.
To calculate the length of the current receive frame the software has to evaluate
When
In the receive HFC-channels
software detects an end of receive frame (
of
is done by setting the bit V_INC_F in the register R_INC_RES_FIFO. If
March 2003 (rev. A)
HFC-E1
½´ ½µ
½
¾
½
and
is stored,
¾
¾
G
Before reading a new frame, a change FIFO operation (write access to
the register R_FIFO) has to be done even if the desired FIFO is already
selected. The change FIFO operation is required to update the internal
buffer of the HFC-E1. Otherwise the first 4 bytes of the FIFO will be
taken from the internal buffer and may be invalid.
is used for the frame which is just received from the E1 interface side of the
¾
the FIFO is totally empty.
reaches
is incremented also the -counters may change because
½´ ¾µ
¾
¾´ ¾µ
Important !
. Thus there are
¾
is the end of frame pointer of the current output frame.
is incremented and
is used for the frame which is just beeing transmitted to the host bus
½
the complete frame has been read.
FIFO handling and HDLC controller
¾
½´ ½µ
must be incremented from the host interface side after the
,
½´ ½µ
½
Data Sheet
¾
¾´ ½µ
is incremented by the HFC-E1 automatically and
is copied as start address of the next frame. This
½
can not be accessed.
,
¾
½´ ¾µ
) and
¾
has to be incremented. If the frame
½
is not incremented. Proper HDLC
and
½
¾´ ¾µ
¾
. Then the current value
½
(see Fig. 4.1).
and
¾
are functions
½
½
Cologne
Chip
135 of 272
¾
¾·½
and
.